Circuit partitioning algorithm for low-power design under area constraints using simulated annealing

A synthesis algorithm is proposed for the design of low-power combinational circuits under area constraints. The algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reducing unnecessary signal transitions. Partitioning is performed through an adaptive simulated annealing algorithm, employing a cost function modelled for low-power consumption under given area constraints. Experiments have been performed for the MCNC benchmark circuits using the power analysis package provided in the the Synopsys Design Analyzer. Results show that the proposed algorithm generates circuits which consume less power than those by the area-optimisation package in Synopsys Design Analyzer and precomputation algorithm