Junctionless Vertical-Si-Nanowire-Channel-Based SONOS Memory With 2-Bit Storage per Cell

This letter reports on a junctionless silicon/oxide/nitride/oxide/silicon memory realized on vertical-Si-nanowire gate-all-around structures with two physical storage nodes per cell. Two physical bits per cell are electrically evaluated by studying the second bit effect and the program/erase speeds, endurance, and retention. The relaxed channel length limitation due to the vertical structure provides more tolerance to overcome the scaling-related reliability issues. In addition, the absence of junctions reduces the process complexity and cost, thus making this device more manufacturable with a very low thermal budget.