Title :
Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric
Author :
Lu, Qiang ; Yeo, Yee Chia ; Yang, Kevin J. ; Lin, Ronald ; Polishchuk, Igor ; King, Tsu-Jae ; Hu, Chenming ; Song, S.C. ; Luan, H.F. ; Kwong, Dim-Lee ; Guo, Xin ; Luo, Zhijiong ; Wang, Xiewen ; Ma, Tso-Ping
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
7/1/2001 12:00:00 AM
Abstract :
P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.
Keywords :
CMOS integrated circuits; MOSFET; chemical vapour deposition; dielectric thin films; integrated circuit technology; leakage currents; rapid thermal processing; silicon compounds; vapour deposition; 14 A; 80 nm; CMOS process; JVD Si/sub 3/N/sub 4/ gate dielectric technology; PMOSFETs; RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technology; Si nitride technologies; Si/sub 3/N/sub 4/; Si/sub 3/N/sub 4/-SiON; SiO/sub 2/; device characteristics; drive current; gate tunneling current; low gate leakage current; p-MOSFETs; p-channel MOSFETs; post-SiO/sub 2/ MOSFET gate dielectric; post-SiO/sub 2/ scaling; CMOS process; CMOS technology; Chemical vapor deposition; Dielectrics; Hafnium; Leakage current; MOSFET circuits; Rapid thermal processing; Silicon; Zirconium;
Journal_Title :
Electron Device Letters, IEEE
