Title :
A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers
Author :
Samueli, Henry ; Daneshrad, Babak ; Joshi, Robindra B. ; Wong, Bennett C. ; Nicholas, Henry T., III
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fDate :
8/1/1991 12:00:00 AM
Abstract :
A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2-μm CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3×4.3 mm2, 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud
Keywords :
CMOS integrated circuits; adaptive filters; digital communication systems; digital filters; echo suppression; equalisers; feedback; subscriber loops; transceivers; 1.2 micron; 2B1Q HDSL transceivers; 2B1Q transceivers; 60 MHz; 64-tap adaptive FIR filter chip; CMOS; HDSL; LMS algorithm; adaptive filter; clock rate; coefficient updating; decision feedback equalizer; echo canceler; filter lengths; high bit rate digital subscriber line; least mean square; symbol rates; Bit rate; Bridge circuits; Communication cables; Copper; Crosstalk; DSL; Decision feedback equalizers; Echo cancellers; Signal to noise ratio; Transceivers;
Journal_Title :
Selected Areas in Communications, IEEE Journal on
