Development of Low-Noise Front-End ASIC for Hybrid CdTe Pixel Detectors

A front-end ASIC with spectroscopic capability was developed to construct a prototype CdTe pixel detector for future use in focusing hard X-ray telescopes. The ASIC is designed for a hybrid configuration, where each CdTe sensor pixel is vertically connected to a corresponding pixel cell fabricated in the readout ASIC. The readout chip consists of a 12 × 12 matrix of identical 270×270 μm² pixel cells, and was implemented with TSMC 0.35 μm CMOS technology. The low noise performance achieved an equivalent noise charge distribution of 50 ±10 e^- . A CdTe pixel detector was mounted on the ASIC using an In/Au-stud bump-bonding technique. The detector was operated in self-trigger mode, and showed good spectral performance with energy resolution of 870 eV (FWHM) at 59.5 keV.