DocumentCode :
1506056
Title :
Corrections to “On the Suitability of a High- 
Gate Dielectric in Nanoscale FinFET CMOS Technology”
Author :
Agrawal, Sanjay ; Fossum, J. G.
Volume :
56
Issue :
12
fYear :
2009
Firstpage :
3245
Lastpage :
3245
Abstract :
In the above titled paper (ibid., vol. 55, no. 7, pp. 1714-1719), the propagation delays in Table III are incorrect, being too long by a factor of two. Furthermore, there was a typo in the table title. The corrected table and title are presented here.
Keywords :
CMOS technology; Computer aided software engineering; Dielectric devices; Electron devices; FinFETs; High K dielectric materials; High-K gate dielectrics; Nanoscale devices; Paper technology; Propagation delay;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2009.2033416
Filename :
5291782
Link To Document :
