DocumentCode :
1506317
Title :
Evolution of engineering change and repair technology in high performance multichip modules at IBM
Author :
Perfecto, Eric D. ; Ray, Sudipta K. ; Wassick, Thomas A. ; Stoller, Herb
Author_Institution :
IBM Microelectron., Hopewell Junction, NY, USA
Volume :
22
Issue :
2
fYear :
1999
fDate :
5/1/1999 12:00:00 AM
Firstpage :
129
Lastpage :
135
Abstract :
In multichip modules (MCMs), engineering changes (EC) are required for both repair of defective chip to chip connections within the module, as well as modification of electrical connections for module performance optimization. With the recent use of complementary metal-oxide-semiconductor (CMOS) chips in IBM´s latest generation of mainframe machines, EC design has been modified to accommodate chips with a much higher number of signal I/Os. Using the previous design methodology of connecting each signal C4 to an EC pad, a large area of the top surface of the module would be required for EC features. This would force increased chip-to-chip wiring length and impact module performance. In addition, larger size MCMs would be required, driving up cost. The new EC approach utilizes top surface thin film wiring in the X and Y directions, which is not pre-connected to any signal C4 pads. The approach used to make desired EC connections is described. New processes were developed to make micro-connections to customize an EC connection, CMOS based MCMs have more than 5× the signal I/Os per chip compared to bipolar devices. As a result of the evolution in EC technology, CMOS chip based MCMs have been successfully designed, built, tested and debugged quickly. They are being used in IBM´s latest generation mainframe machines
Keywords :
CMOS integrated circuits; integrated circuit packaging; lead bonding; multichip modules; wiring; CMOS chips; IBM; chip-to-chip wiring length; defective chip to chip connections; electrical connections; engineering change; mainframe machines; multichip modules; repair technology; signal I/Os; thermal conduction module; top surface thin film wiring; CMOS technology; Costs; Design methodology; Joining processes; Multichip modules; Optimization; Signal design; Signal generators; Transistors; Wiring;
fLanguage :
English
Journal_Title :
Advanced Packaging, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3323
Type :
jour
DOI :
10.1109/6040.763183
Filename :
763183
Link To Document :
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