Unified VLSI systolic array design for LZ data compression

Author

Hwang, Shih Arn ; Wu, Cheng Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

9

Issue

4

fYear

2001

Firstpage

489

Lastpage

499

Abstract

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup.

Keywords

CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; high-speed integrated circuits; integrated circuit design; logic design; parallel algorithms; systolic arrays; 0.8 micron; CMOS chip; LZ data compression; Lempel-Ziv data compression; data compression algorithm; hardware implementation; optimal linear array; parallel 2D systolic-arrays; scalable array architecture; unified VLSI systolic array design; CADCAM; Compression algorithms; Computer aided manufacturing; Data communication; Data compression; Hardware; Redundancy; Systolic arrays; Testing; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.931226

Filename

931226