DocumentCode

1506626

Title

Correction to "Design of synchronous and asynchronous variable-latency pipelined multipliers"

Author

Olivieri, Mauro

Author_Institution

University of Rome "La Sapienza"

Volume

9

Issue

4

fYear

2001

Firstpage

558

Lastpage

559

Keywords

Delay; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2001.931231

Filename

931231