A 7.3 μW decimation filter for 15 bit 25 kHz audio ΣΔ modulator

Author

Ince, Murat ; Akcakaya, F. Melih ; Dundar, Gunhan

Author_Institution

Bogazici Univ., Istanbul, Turkey

fYear

2014

fDate

4-6 May 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18 μm technology. It consumes 7.25 μW for 15 bit Audio ΣΔ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth.

Keywords

CMOS integrated circuits; FIR filters; audio equipment; low-power electronics; sigma-delta modulation; CIC filter; CMOS technology; FIR filter; GAM algorithm; audio sigma-delta modulator; bandwidth 25 kHz; canonical signed digit representation; decimation filter; finite impulse response filter; frequency 1.6 MHz; half-band filter; low power filter; multiplierless filter architecture; multistage CIC structure; oversampling analog-digital converters; polyphase structure; power 7.25 muW; Filtering algorithms; Finite impulse response filters; IIR filters; Modulation; Power demand; Power filters; decimation; filter; low power; sigma-delta;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2014 IEEE

Conference_Location

Monaco

Type

conf

DOI

10.1109/FTFC.2014.6828601

Filename

6828601