Title :
Performance estimation of Si/SiGe hetero-CMOS circuits
Author :
Hagelauer, R. ; Ostermann, T. ; Konig, U. ; Glück, M. ; Höck, G.
Author_Institution :
Dept. of Microelectron. Syst., Johannes Kepler Univ., Linz, Austria
fDate :
1/30/1997 12:00:00 AM
Abstract :
Semiquantitative performance extrapolation of Si/SiGe heterostructure p- and n-channel devices point to transconductances above 100 mS/mm and cutoff frequencies around 200 GHz. Circuits such as inverters, logic arrays (e.g. NAND-gates) and flip-flops are simulated with feature sizes down to 0.05 μm showing a promising performance potential. Delay times of 2.5 and 0.5 ps/stage are obtained for an inverter chain at a power supply voltage of 1 and 2.5 V respectively
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; Ge-Si alloys; NAND circuits; delays; elemental semiconductors; flip-flops; logic arrays; logic gates; semiconductor materials; silicon; 0.05 to 0.3 micron; 0.5 to 2.5 ps; 1 to 2.5 V; 100 to 1070 mS/mm; 200 GHz; NAND gates; Si-SiGe; Si/SiGe hetero-CMOS circuits; cutoff frequencies; delay times; flip-flops; inverters; logic arrays; n-channel devices; p-channel devices; performance estimation; transconductances;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19970166
