Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array

Author

Wang, Kuan-Ti ; Hsueh, Fang-Chang ; Lu, Yu-Lun ; Chiang, Tsung-Yu ; Wu, Yi-Hong ; Liao, Chia-Chun ; Yen, Li-Chen ; Chao, Tien-Sheng

Author_Institution

Dept. of Electrophys., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

33

Issue

6

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

839

Lastpage

841

Abstract

This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 μs and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.

Keywords

logic gates; semiconductor device reliability; thin film transistors; NOR-type flash array; SSI; WSG; data retention tests; high programming efficiency; memory window; optimal reliability; source-side injection; time 10 mus; time 30 ms; voltage 3 V; word length 2 bit; wrapped-select-gate SONOS TFT memory; wrapped-selected-gate SONOS thin-film transistor memory; Charge carrier processes; Logic gates; Programming; SONOS devices; Silicon; Thin film transistors; Source-side injection (SSI); thin-film transistor memory; two-bit/cell; wrapped-selected-gate (WSG)-SONOS;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2012.2192090

Filename

6194261