DocumentCode :
1507911
Title :
Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM
Author :
Kim, Heesang ; Oh, Byoungchan ; Son, Younghwan ; Kim, Kyungdo ; Cha, Seon-Yong ; Jeong, Jae-Goan ; Hong, Sung-Joo ; Shin, Hyungcheol
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
Volume :
58
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
1643
Lastpage :
1648
Abstract :
To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and the activation energy for two trap models, i.e., the metastable and oxide trap models. Measuring the tret of VRT cells for various bias and temperature conditions, the dependence of activation energy differences in tret on bias at high and low retention states was extracted. Furthermore, the dependence of the electric field on bias at high and low retention states was also extracted. Using those parameters, we successfully distinguished the two types of trap models.
Keywords :
DRAM chips; DRAM; VRT cells; dynamic random access memory; metastable trap models; oxide trap models; variable retention time phenomenon; Electrical engineering; Electron traps; Leakage current; Logic gates; Mathematical model; Random access memory; Transistors; Activation energy; dynamic random access memory (DRAM); gate-induced drain leakage (GIDL); random telegraph noise (RTN); variable retention time (VRT);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2011.2125964
Filename :
5759766
Link To Document :
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