DocumentCode :
15081
Title :
Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption
Author :
Daejin Park ; Tag Gon Kim
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Volume :
22
Issue :
5
fYear :
2014
fDate :
May-14
Firstpage :
1187
Lastpage :
1191
Abstract :
The bit-line sense amplifier (S/A) for on-chip flash memory compares cell current with reference current to identify data that are programmed. The S/A for 0 (erased) cell data consumes a large sink current, which is greater than off-current for 1 (programmed) cell data. This brief proposes a built-in write/read path based on binary inversion methods to reduce the sensing current of S/A. An original binary code is programmed into flash memory with an inverted binary code based on the proposed bit inversion techniques. The de-inversion hardware, which is implemented with small logic gates to restore original binary data, only consumes logic current instead of analog sink current in the S/A. The proposed techniques are evaluated for the DSPStone benchmark and are applied to the modified S/A for ARM Cortex-M3-based microcontroller with 128-kB on-chip flash memory based on a 0.18-um EEPROM technology. The circuit-level simulation result for the DSPStone benchmark shows that a newly implemented chip with the S/A based on the proposed technique consumes approximately less than 22% of the operating power that conventional S/A uses.
Keywords :
EPROM; amplifiers; binary codes; electric sensing devices; flash memories; logic gates; microcontrollers; ARM Cortex-M3-based microcontroller; DSPStone benchmark; EEPROM technology; S-A; analog sink current; binary data restoration; bit inversion technique; bit-line sense amplifier; built-in binary code inversion technique; built-in write-read path; circuit-level simulation; current sensor; data consumption; deinversion hardware; logic current consumption; logic gate; on-chip flash memory sense amplifier; reduced read current consumption; reference cell current; size 0.18 mum; storage capacity 128 Kbit; Bit-line sense amplifier; data-pattern-dependent sensing; flash memory; low dynamic power; read-path; sense circuit; sense circuit.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2013.2265894
Filename :
6549111
Link To Document :
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