Third-order cascaded sigma-delta modulators

A sigma-delta modulator architecture wherein third-order noise shaping is achieved with relatively modest constraints on device matching is explored. The architecture is based on a cascade of a second-order modulator stage followed by a first-order stage, both using 1-b quantization. To improve the dynamic range, the input to the second stage is generated as an asymmetrically weighted error signal from the first stage. An analytical model for assessing the performance and device matching requirements of cascaded architectures is introduced, and computer simulations are used to verify the approximations made in this model. The analytical model is used to show that the proposed architecture offers performance comparable to other third-order cascaded sigma-delta modulator topologies, while being less sensitive to device matching errors