DocumentCode
1508401
Title
“Depletion isolation effect” of surrounding gate transistors
Author
Terauchi, Mamoru ; Shigyo, Naoyuki ; Nitayama, Akihiro ; Horiguchi, Fumio
Author_Institution
Adv. Semicond. Device Lab., Toshiba Corp., Kawasaki, Japan
Volume
44
Issue
12
fYear
1997
fDate
12/1/1997 12:00:00 AM
Firstpage
2303
Lastpage
2305
Abstract
Sub-half-micron surrounding gate transistors (SGTs) were fabricated and their current-voltage (I-V) characteristics were investigated. Even in a SGT whose Si pillar is not fully depleted (e.g., 0.6 μm SGT), by using the lower diffusion layer of the Si pillar as drain and applying sufficiently high voltage, I-V characteristics inherent to fully depleted devices (i.e. subthreshold swing as low as 60 mV/dec., lowered threshold voltage independent of substrate bias voltage) were observed (“depletion isolation effect”)
Keywords
CMOS integrated circuits; MOSFET; 0.6 micron; CMOS twin tub process; I-V characteristics; Si; Si pillar; current-voltage characteristics; depletion isolation effect; sub-half-micron transistors; surrounding gate transistors; vertical transistor; CMOS process; Electric variables; Etching; Fabrication; Laboratories; Low voltage; Nonvolatile memory; Random access memory; Substrates; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.644659
Filename
644659
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