Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices

Through-silicon vias (TSVs) have two negative effects in the design of three-dimensional integrated circuits (3-D ICs). First, TSV insertion leads to silicon area overhead. In addition, nonnegligible TSV capacitance causes delay overhead in 3-D signal paths. Therefore, obtaining all benefits such as wirelength reduction and performance improvement from 3-D ICs is highly dependent on TSV size and capacitance. Meanwhile, TSVs are downscaled to minimize their negative effects, and sub-micron TSVs are expected to be fabricated in the near future. At the same time, the devices are also downscaled beyond 32 nm and 22 nm, so future 3-D ICs will very likely be built with sub-micron TSVs and advanced device technologies. In this paper, we investigate the impact of sub-micron TSVs on the quality of today and future 3-D ICs. For future process technologies, we develop 22 nm and 16 nm libraries. Using these future process libraries and an existing 45 nm library, we generate 3-D IC layouts with different TSV sizes and capacitances and study the impact of sub-micron TSVs thoroughly.