Efficient sensor for robust low-power design in nano-CMOS technologies

Conventional design methods add pessimistic safety margins to mitigate increased variability in scaled technologies that incur high power and performance losses. An efficient sensor design is presented that can significantly reduce design margins yet provide robust circuit operation. The proposed design uses the delay of the master latch of a conventional flip-flop to predetect timing failures and enable low-power error-free operation. HSPICE simulation of a 45 nm 16 ?? 16 carry save multiplier indicates a 37% reduction in the total power consumption for the proposed design compared to a conventional worst case design when subjected to high statistical variability. Similarly, gate level simulations show a 26% reduction in the total power consumption of a 32 nm 32-bit carry select adder when subjected to temperature variations.