DocumentCode
1509380
Title
Evolutionary graph generation with terminal-colour constraint for heterogeneous circuit synthesis
Author
Natsui, M. ; Aoki, T. ; Higuchi, T.
Author_Institution
Higuchi Lab., Tohoku Univ., Sendai, Japan
Volume
37
Issue
13
fYear
2001
fDate
6/21/2001 12:00:00 AM
Firstpage
808
Lastpage
810
Abstract
A novel graph-based evolutionary optimisation technique that can be used to synthesise heterogeneous circuits consisting of various different components is proposed. The key idea is to introduce “circuit graphs with coloured terminals” for modelling heterogeneous architectures. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit
Keywords
adders; circuit optimisation; evolutionary computation; graph colouring; logic CAD; circuit graphs; evolutionary graph generation; heterogeneous circuit synthesis; optimisation technique; radix-4 signed-digit full adder circuit; terminal-colour constraint;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010587
Filename
933390
Link To Document