• DocumentCode
    1509392
  • Title

    Compact central arbiters for memories with multiple read/write ports

  • Author

    Omori, N. ; Mattausch, H.J.

  • Author_Institution
    Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
  • Volume
    37
  • Issue
    13
  • fYear
    2001
  • fDate
    6/21/2001 12:00:00 AM
  • Firstpage
    811
  • Lastpage
    813
  • Abstract
    Fast and compact central arbiter circuits for detection and regulation of access conflicts in memories with multiple ports are proposed. A layout study in 0.5 μm, 2 metal CMOS technology verifies that area-overhead and access time penalty are small up to 32 ports
  • Keywords
    CMOS logic circuits; asynchronous circuits; integrated circuit layout; multiport networks; 0.5 micron; access conflicts; access time penalty; area-overhead; central arbiter circuits; layout study; multiple read/write ports; two-metal CMOS technology;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010583
  • Filename
    933392
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1509392