12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s

Author

Promitzer, Gilbert

Author_Institution

Austria Mikro Syst. Int. AG, Austria

Volume

36

Issue

7

fYear

2001

fDate

7/1/2001 12:00:00 AM

Firstpage

1138

Lastpage

1143

Abstract

Based on a conventional successive approximation ADC architecture, a new and faster solution is presented. The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element. A switching circuit is implemented to allow a wider input voltage range of the ADC. Together with a self-timed comparator, the power consumption is noticeably reduced while at the same time the sampling rate is doubled. Smaller input and reference capacitances reduce the requirements on the input and reference sources, respectively. Additionally, a widely clock-duty-cycle-independent control logic improves the applicability of the converter cell, especially for systems on chip. Results of measurements confirm the theoretical improvements

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; switched capacitor networks; 0.6 micron; 12 bit; 15 mW; 21 pF; 3 to 5.5 V; CMOS ADC; clock-duty-cycle-independent control logic; fully differential SC ADC; low-power ADC; noncalibrating ADC; power consumption reduction; sampling rate; self-timed comparator; successive approximation ADC architecture; switched capacitor ADC; switching circuit; transmission gates; Capacitance; Capacitors; Clocks; Control systems; Energy consumption; Logic; Sampling methods; Switching circuits; System-on-a-chip; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.933473

Filename

933473