• DocumentCode
    1509898
  • Title

    Design verification of FPGA implementations

  • Author

    Chen, Xiao-Tao ; Huang, Wei-Kang ; Park, Nohpill ; Meyer, Fred J. ; Lombardi, Fabrizio

  • Author_Institution
    Texas A&M Univ., College Station, TX, USA
  • Volume
    16
  • Issue
    2
  • fYear
    1999
  • Firstpage
    66
  • Lastpage
    73
  • Abstract
    This approach uses the criterion of equivalent classes to establish the equivalence between two circuits and designs. Combining simulation and automatic test pattern generation, it exploits similarities among designs to assess logical equivalence quickly and reliably
  • Keywords
    automatic test pattern generation; equivalent circuits; field programmable gate arrays; FPGA implementations; automatic test pattern generation; design verification; equivalence; logical equivalence; Automatic test pattern generation; Binary decision diagrams; Character generation; Circuit simulation; Circuit testing; Computational modeling; Design optimization; Field programmable gate arrays; Logic design; Logic testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.765205
  • Filename
    765205
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1509898