DocumentCode :
1509905
Title :
The hybrid field-programmable architecture
Author :
Kaviani, Alireza ; Brown, Stephen
Author_Institution :
Toronto Univ., Ont., Canada
Volume :
16
Issue :
2
fYear :
1999
Firstpage :
74
Lastpage :
83
Abstract :
The authors propose a new architecture that combines two existing technologies: lookup-table-based FPGAs and complex programmable logic devices based on PLA-like blocks. Their mapping results indicate that on average LUT-based FPGAs require 78% more area than their hybrid FPGA, while providing roughly the same circuit depth
Keywords :
field programmable gate arrays; logic design; programmable logic devices; field-programmable architecture; lookup-table-based FPGAs; programmable logic devices; Circuit testing; Computer architecture; Field programmable gate arrays; Inverters; Logic design; Logic devices; Logic testing; Programmable logic arrays; Programmable logic devices; Table lookup;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.765206
Filename :
765206
Link To Document :
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