Title :
A virtual clock enhancement method for DDS using an analog delay line
Author :
Richter, Raik ; Jentschel, Hans-Joachim
Author_Institution :
Inst. of Traffic Inf. Syst., Tech. Univ. Dresden, Germany
fDate :
7/1/2001 12:00:00 AM
Abstract :
In this paper, we describe an analog delay line (DL) used for virtual clock enhancement in a direct digital synthesis (DDS). The novelty of the proposed method is the immediate application of the output signal of the phase accumulator for the generation of the desired frequency. To obtain the necessary spectral purity of the generated frequency, additional digital signal processing (DSP) based on a delay-locked loop (DLL) and noise shaping is applied. The consequences of nonlinear effects within the DL for the spectral performance of the DDS are explained
Keywords :
CMOS integrated circuits; delay lines; delay lock loops; direct digital synthesis; mixed analogue-digital integrated circuits; timing; 0.8 micron; 100 MHz; 300 mW; CMOS-based ASIC; DDS; DLL; DSP; analog delay line; delay-locked loop; digital signal processing; direct digital synthesis; noise shaping; nonlinear effects; phase accumulator output signal; spectral purity; virtual clock enhancement method; Clocks; Delay lines; Digital signal processing; Frequency synthesizers; Jitter; Noise reduction; Noise shaping; Read only memory; Signal generators; Signal synthesis;
Journal_Title :
Solid-State Circuits, IEEE Journal of
