A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS

Author

Barale, F. ; Sen, P. ; Sarkar, S. ; Pinel, S. ; Laskar, J.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

20

Issue

7

fYear

2010

fDate

7/1/2010 12:00:00 AM

Firstpage

411

Lastpage

413

Abstract

This letter presents, for the first time, a 60 GHz four-channel standard compatible heterodyne frequency synthesizer solution with low-cost reference signal. The presented PLL features a dual-core varactor-based LC cross-coupled voltage-controlled oscillator (VCO). The measured phase noise is -80.1 dBc/Hz at 1 MHz offset, and it is limited by the phase noise of the reference signal. The measured output spectrum shows spur suppression higher than 32 dBc. Using the lowest reference frequency to date (27 MHz), the presented PLL is suitable for applications in low cost fully integrated multi-gigabit 60 GHz CMOS radio transceivers.

Keywords

CMOS integrated circuits; RLC circuits; frequency synthesizers; integrated circuit noise; millimetre wave integrated circuits; phase noise; varactors; voltage-controlled oscillators; CMOS radio transceivers; PLL; dual-core varactor-based LC cross-coupled VCO; frequency 50 GHz; frequency 60 GHz; heterodyne frequency synthesizer; low-cost reference signal; measured phase noise; phase-locked loop; voltage-controlled oscillator; CMOS integrated circuits; frequency divider; millimeter-wave circuits; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2010.2049444

Filename

5481967