High-Performance Poly-Si Vertical Nanowire Thin-Film Transistor and the Inverter Demonstration

Author

Le, T.T. ; Yu, H.Y. ; Sun, Y. ; Singh, N. ; Zhou, X. ; Shen, N. ; Lo, G.Q. ; Kwong, D.L.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

Volume

32

Issue

6

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

770

Lastpage

772

Abstract

In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both Nand P-TFT devices (with gate length down to 100 nm and a wire diameter of ~30 nm) exhibit good transistor performance, e.g., high I_on/I_off ratio of >; 10⁶, low subthreshold slope (SS ~ 100 mV/dec), and reasonable drain-induced barrier lowering [(DIBL); ~50 mV/V] with a wire diameter of ~30 nm. Inverters have been successfully fabricated based on the poly-Si NW TFTs, exhibiting well-behaved transfer characteristics.

Keywords

CMOS logic circuits; NAND circuits; elemental semiconductors; logic gates; nanowires; silicon; thin film transistors; CMOS-compatible process; DIBL; NW poly-silicon TFT; Nand P-TFT devices; Si; drain-induced barrier lowering; gate length; gate-all-around vertical nanowire; high-performance poly-silicon vertical nanowire thin-film transistor; inverter demonstration; polycrystalline silicon thin-film transistors; subthreshold slope; transistor performance; well-behaved transfer characteristics; wire diameter; Inverters; Logic gates; Performance evaluation; Switches; Thin film transistors; Wire; Gate-all-around (GAA); nanowire (NW); polycrystalline silicon (poly-Si); thin-film transistors (TFTs);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2136315

Filename

5763753