Title :
Automated Design Error Localization in RTL Designs
Author :
Jenihhin, Maksim ; Tsepurov, Anton ; Tihhomirov, Valentin ; Raik, Jaan ; Hantson, Hanno ; Ubar, Raimund ; Bartsch, Gunter ; Escobar, JorgeHernan Meza ; Wuttke, Heinz-Dietrich
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
Abstract :
This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.
Keywords :
formal verification; hardware description languages; HDL; RTL designs; automated design error localization; functional verification; hardware description language; post-silicon validation; register transfer level; Computer bugs; Design methodology; Error analysis; Hardware design languages; Registers; Verification;
Journal_Title :
Design & Test, IEEE
DOI :
10.1109/MDAT.2013.2271420
