Improved delay-line based digital PWM for DC-DC converters

An improved delay-line based digital pulse-width modulator (DPWM) architecture for DC-DC converters is presented to significantly enhance the area and power efficiency. In order to reuse the delay elements, the proposed scheme utilises the rising delay and falling delay to achieve the coarse and fine resolution of the DPWM, respectively. An 8-bit DPWM employing the improved architecture was implemented in SMIC standard 0.13 μm CMOS process. Simulation results indicate that a 90 of size saving is achieved for 8-bit resolution compared to the conventional method. Owing to the decrease in the number of delay elements, power consumption is also reduced.