An Accurate Charge-Control-Based Approach for Noise Performance Assessment of a Symmetric Tied-Gate InAlAs/InGaAs DG-HEMT

Author

Bhattacharya, Monika ; Jogi, Jyotika ; Gupta, R.S. ; Gupta, Mridula

Author_Institution

Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India

Volume

59

Issue

6

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

1644

Lastpage

1652

Abstract

Noise performance analysis of a symmetric tied-gate InAlAs/InGaAs double-gate (DG) high-electron mobility transistor (HEMT) is presented using an accurate charge-control-based noise model. The intrinsic noise coefficients are obtained in terms of which the various noise performance parameters, including, the noise resistance and the Minimum noise figure are evaluated. The effect of the parasitic source and gate resistances has also been incorporated to obtain extrinsic minimum noise figure. The results obtained show improved noise performance of DG-HEMT as compared to the single-gate HEMT in terms of lower minimum noise figure. The analytical results obtained are validated with the ATLAS device simulation results as well as with the experimental and Monte Carlo simulation data.

Keywords

III-V semiconductors; Monte Carlo methods; gallium arsenide; high electron mobility transistors; indium compounds; semiconductor device models; ATLAS device simulation; InAlAs-InGaAs; Monte Carlo simulation data; charge-control-based noise model; extrinsic minimum noise figure; intrinsic noise coefficients; noise performance assessment; single-gate HEMT; symmetric tied-gate DG-HEMT; symmetric tied-gate double-gate high-electron mobility transistor; Correlation; Indium gallium arsenide; Logic gates; Noise; Performance evaluation; Resistance; Charge control; InAlAs/InGaAs; double-gate (DG); high-electron mobility transistor (HEMT); minimum noise figure; noise resistance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2012.2190738

Filename

6196214