Delay-optimal clustering targeting low-power VLSI circuits

This paper presents a delay-optimal clustering algorithm for minimizing the power dissipation in a very large scale integration (VLSI) circuit. Traditional approaches for delay-optimal clustering are based on Lawler´s clustering algorithm which makes no attempt to explore alternative clustering solutions that have the same delay but lower power implementations. Our algorithm implicitly enumerates alternate clusterings and selects a clustering solution which has the same delay, but the lowest power dissipation. For tree circuits, the proposed algorithm produces delay- and power-optimal clustering, whereas for nontree circuits it produces delay-optimal clustering with significantly reduced power dissipation. The proposed mechanism can be used to generate power minimized clusters for various applications such as preprocessing designs for partitioning, clustering logic during synthesis, etc. The mechanism can also be deployed hierarchically to generate circuit partitioning solutions directly