Title :
COBRA: a 100-MOPS single-chip programmable and expandable FFT
Author :
Chen, Tom ; Sunada, Glen ; Jin, Jian
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
fDate :
6/1/1999 12:00:00 AM
Abstract :
This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.2 /spl mu/s, far surpassing the performance of any existing FFT systems.
Keywords :
digital arithmetic; digital signal processing chips; fast Fourier transforms; programmable circuits; COBRA; bit-serial arithmetic; clock rate; complex FFT transform; dynamic reconfiguration; expandable FFT; optimized column fast Fourier transform architecture; single-chip programmable FFT; Arithmetic; CMOS technology; Costs; Design for testability; Digital signal processing chips; Discrete Fourier transforms; Fast Fourier transforms; Signal processing algorithms; Speech analysis; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
