• DocumentCode
    1512366
  • Title

    Design and application of the interlayer van der Pauw resistor alignment bridge

  • Author

    Feldbaumer, David Wm ; Varker, Charles J. ; Griswold, Mark ; Allen, Bruce D.

  • Author_Institution
    Motorola Inc., Mesa, AZ, USA
  • Volume
    3
  • Issue
    4
  • fYear
    1990
  • fDate
    11/1/1990 12:00:00 AM
  • Firstpage
    206
  • Lastpage
    215
  • Abstract
    The interlayer van der Pauw (VDP) resistor alignment bridge combines the sheet resistor and registration-sensitive bridge into one unified structure. As a result of symmetry, it does not require the width corrections resulting from image exposure and etch variations typical of linear resistor structures. It uses minimum area and pad count and provides orthogonal registration measurements. Bridges designed for 1.5-μm feature size with body dimensions of 18 and 21 μm and a tap length to width ratio of 0.5 show a sensitivity of 34-38 mV/μm at 10 mA. Registration errors of 0.2 μm have been measured with an error of less than 10%. A good statistical correlation has been obtained between drawn and measured registration offsets. The correlation between the VDP bridge and the optical vernier is within ±2% using a vernier spacing of 0.125 μm. These results clearly indicate that the VDP bridge has the potential to provide accurate measurements of photo mask registration with the precision required for very large scale integration (VLSI) processing. The application of the VDP resistor bridge for interlayer registration using standard production procedures is described. Measurement precision and accuracy are discussed along with some fundamental bridge-design considerations
  • Keywords
    VLSI; bridge circuits; distance measurement; integrated circuit manufacture; integrated circuit testing; photolithography; 1.5 micron; VLSI; interlayer registration; interlayer van der Pauw resistor alignment bridge; orthogonal registration measurements; photo mask registration; registration-sensitive bridge; sheet resistor; very large scale integration; Bridge circuits; Density estimation robust algorithm; Etching; Integrated circuit measurements; Manufacturing processes; Optical sensors; Production; Resistors; Testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/66.61970
  • Filename
    61970