Energy-Efficient Design Methodologies: High-Performance VLSI Adders

Author

Zeydel, Bart R. ; Baran, Dursun ; Oklobdzija, Vojin G.

Author_Institution

Plato Networks Inc., Santa Clara, CA, USA

Volume

45

Issue

6

fYear

2010

fDate

6/1/2010 12:00:00 AM

Firstpage

1220

Lastpage

1233

Abstract

Energy-efficient design requires exploration of available algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper, methodology for energy-efficient design applied to 64-bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino logic families, is presented. We also examined 65 nm, 45 nm, 32 nm, and 22 nm technology nodes to explore the applicability of the results in deep submicron technologies. By applying energy-delay tradeoffs on various levels, we developed adder topology yielding up to 20% performance improvement and 4.5× energy reduction over existing designs.

Keywords

CMOS logic circuits; VLSI; adders; logic design; CMOS compound domino logic family; VLSI adders; adder topology; circuit design techniques; circuit sizing; deep submicron technology; dynamic CMOS; energy reduction; energy-delay tradeoffs; energy-efficient design methodologies; recurrence structures; size 22 nm; size 32 nm; size 45 nm; size 65 nm; static CMOS; system constraints; wire tradeoffs; Adders; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Circuit synthesis; Design methodology; Energy efficiency; Logic design; Very large scale integration; Wire; Arithmetic and logic structures; VLSI; computer arithmetic; energy-efficient design; high-speed arithmetic; low-power design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2048730

Filename

5482517