Simulation approach for achieving layout independent polysilicon gate etching

Profile and dimension control mechanism in polysilicon gate etching is studied systematically by the use of two-dimensional (2-D) etching topography simulator. Reaction rates are calculated by taking into account interactions between incoming ion/radical fluxes and an ever-changing macroscopic adsorbed particle layer on the film surface. A qualitative guideline is presented for achieving both anisotropic etched-profile formation and the dimension difference minimization between the inner line pattern width w_i and the outermost line pattern width w_e in repeated line and space configuration. When w_c>w_i>w_m (resist mask width), following two possible measures are necessary. One is to make gas pumping speed large for shortening the residence time of depositive radicals. The other is to make cathode temperature high for lowering sticking coefficient of depositive radicals. These are effective in reducing the amount of deposited film especially at the sidewall of external part of the outermost line pattern (SEP). Higher gas pressure is also effective in sputtering the deposited film especially at SEP