Title :
Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects
Author :
Bandyopadhyay, Tapobrata ; Han, Ki Jin ; Chung, Daehyun ; Chatterjee, Ritwik ; Swaminathan, Madhavan ; Tummala, Rao
Author_Institution :
Microsyst. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fDate :
6/1/2011 12:00:00 AM
Abstract :
3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.
Keywords :
MOS capacitors; capacitance; integrated circuit interconnections; integrated circuit modelling; three-dimensional integrated circuits; 3D integration; MOS capacitance effects; TSV MOS capacitance; heterogeneous integration; interconnect length; metal oxide semiconductor capacitance effect; power distribution network; rigorous electrical modeling; signal distribution network; through silicon vias; variable capacitor; wiring delay; Capacitance; Integrated circuit modeling; Logic gates; Mathematical model; Silicon; Substrates; Through-silicon vias; 3-D integration; interconnection modeling; parametric study; power distribution network; through silicon via; variable capacitance;
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2011.2120607
