DocumentCode
1512916
Title
Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS
Author
De Wit, Pieter ; Gielen, Georges
Author_Institution
Dept. of Electr. Eng., Katholieke Univ. Leuven, Leuven, Belgium
Volume
47
Issue
7
fYear
2012
fDate
7/1/2012 12:00:00 AM
Firstpage
1757
Lastpage
1767
Abstract
Continuous scaling to smaller CMOS nodes has enlarged transistor degradation effects, reducing the long-term reliability of integrated circuits. This paper addresses the reliability of a high-voltage xDSL line driver and uses a failure-resilient topology to combine both optimal performance and guaranteed reliability, as verified by simulations in a predictive 32 nm CMOS technology. In addition, to illustrate the self-healing concept, a failure-resilient line driver with reconfigurable output stage, on-chip degradation monitors and system controller, resulting in a guaranteed power efficiency even in the presence of transistor degradation, has been implemented in 90 nm CMOS. Preservation of the power efficiency is verified experimentally using voltage-overstressing and temperature variation measurements.
Keywords
CMOS integrated circuits; digital subscriber lines; driver circuits; integrated circuit reliability; transistors; CMOS node technology; degradation-resilient design; failure-resilient line driver topology; high-voltage xDSL line driver; integrated circuit reliability; on-chip degradation monitoring; power efficiency; reconfigurable output stage; self-healing xDSL line driver; size 90 nm; temperature variation measurement; transistor degradation effect; voltage-overstressing; CMOS integrated circuits; Degradation; Electric breakdown; Human computer interaction; Integrated circuit reliability; Transistors; Degradation-resilient design; hot carrier injection; line driver; negative bias temperature instability;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2012.2191328
Filename
6197241
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