Reduced switching loss pulse width modulation technique for three-level diode clamped inverter

Multilevel inverters are used to reduce the harmonics and to achieve high-voltage, high-power capability but switching losses are increased because of increased device count. Switching losses can be reduced by either soft switching techniques or by modifying modulation technique employing space vector-based PWM techniques or sinusoidal PWM-based techniques. In this study, a carrier-based closed-loop control technique has been developed to reduce the switching losses based on insertion of `no switching` zone within each half cycle of fundamental wave. It effectively reduces the switching losses of three-level inverter without need of any complex mathematical expressions as involved in space vector-based techniques. An improvement of about 5` in efficiency for a switching frequency of 5`kHz is observed with proposed technique over conventional SPWM technique based on efficiency improvement factor (EIF). Simulation and experimental results are presented to validate the proposed technique.