A two-input, one-output bit-scalable architecture for fuzzy processors

Automatic synthesis of fuzzy controllers for commercial microprocessors is already available. For dedicated controllers, however, automatic synthesis is still in development. The problem is that when designers create dedicated architectures to solve specific problems, they don´t consider the possibility of expanding or reducing the internal functional units. The absence of a flexible architecture that fits different applications without the use of expensive solutions has been one of the barriers to making automatic synthesis feasible. In this article we present an architecture suitable for automatic synthesis of digital fuzzy controllers. The main parameters that define the dimensions of the internal units are the number of bits for input and output and the number of bits of input and output membership functions. Our architecture imposes no limitations on the number of rules comprising the knowledge base