Memory access optimisation for reconfigurable systems

Memory access optimisation for FPGA-based reconfigurable systems with a hierarchy of on-chip and off-chip (external) memory to speed up applications limited by memory access speed are discussed. Most of the techniques are also valid for dedicated embedded systems and system-on-a-chip (SoC) designs. The approach involves two kinds of optimisation: first, methods to reduce the number of accesses by caching repeatedly used values are considered. The notion of vector access equivalence is introduced to form the basis of techniques employing FPGA storage as shift registers for caching. Larger data sets can be stored, if possible, in FPGA on-chip RAMs; RAM inference, a technique to automatically extract small on-chip RAMs to reduce external memory accesses is presented. Secondly, the authors aim to minimise the time spent on accesses to bandwidth-limited external memory, by scheduling as many accesses in parallel as possible. They present a technique which optimally allocates program arrays to memory banks, thereby minimising the overall access time. It also determines the most effective addressing mode for memory which can be accessed using different bitwidths