Title :
Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate
Author :
Song, Yi ; Xu, Qiuxia ; Luo, Jun ; Zhou, Huajie ; Niu, Jiebin ; Liang, Qingqing ; Zhao, Chao
Author_Institution :
Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China
fDate :
7/1/2012 12:00:00 AM
Abstract :
We demonstrate high-performance silicon-nanowire gate-all-around MOSFETs (GAA SNWFETs) fabricated on bulk Si by a novel top-down complementary MOS-compatible method. The fabricated nand p-type GAA SNWFETs of ~50-nm gate length and of ~6-nm diameter show superior device performance, i.e., driving capability of 2.6 × 103/2.9 × 103 μA/μm at |VD| = |VG - Vt| = 1.0 V, Ion/Ioff ratio as high as 5 × 108/109, and excellent short-channel-effect immunity with subthreshold slope of 67/64 mV/dec and drain-induced barrier lowering of 6 mV/V, respectively. GAA SNWFETs and FinFETs fabricated on bulk Si were also compared by the investigation of both experiments and Technology Computer Aided Design simulation. The superiority of GAA SNWFETs over FinFETs is evidenced in this paper.
Keywords :
MOSFET; nanofabrication; nanowires; technology CAD (electronics); FinFET; SNWFET; Si; bulk silicon substrate; drain induced barrier lowering; driving capability; performance breakthrough; short channel effect immunity; silicon nanowire gate-all-around MOSFET; size 50 nm; size 6 nm; subthreshold slope; technology computer aided design simulation; top down complementary MOS-compatible method; Fabrication; FinFETs; Logic gates; Performance evaluation; Silicon; Substrates; Bulk substrate; Si nanowire; fabrication; gate all around (GAA); metal–oxide–semiconductor field-effect transistors (MOSFETs);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2012.2194785