DocumentCode
1513684
Title
Scaling SOI MESFETs to 150-nm CMOS Technologies
Author
Lepkowski, William ; Ghajar, M. Reza ; Wilk, Seth J. ; Summers, Nicholas ; Thornton, Trevor J. ; Fechner, Paul S.
Author_Institution
Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ, USA
Volume
58
Issue
6
fYear
2011
fDate
6/1/2011 12:00:00 AM
Firstpage
1628
Lastpage
1634
Abstract
Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT >; 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ~70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <; 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200-300 nm.
Keywords
CMOS integrated circuits; MOSFET; Schottky gate field effect transistors; silicon-on-insulator; CMOS technology; MESFET gate length; SOI MESFET scaling; current drive; metal-semiconductor field-effect transistor; partially depleted silicon-on-insulator complementary metal-oxide semiconductor technology; short-channel effect; size 150 nm; CMOS integrated circuits; CMOS process; Electric breakdown; Layout; Logic gates; MESFETs; Metal–semiconductor field-effect transistors (MESFETs); Schottky junction; partially depleted (PD); silicon-on-insulator (SOI);
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2011.2125965
Filename
5765667
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