DocumentCode
1513851
Title
Graph-theory-based simplex algorithm for VLSI layout spacing problems with multiple variable constraints
Author
Wang, Lih-Yang ; Lai, Yen-Tai
Author_Institution
Dept. of Electron. Eng., Southern Taiwan Univ. of Technol., Tainan, Taiwan
Volume
20
Issue
8
fYear
2001
fDate
8/1/2001 12:00:00 AM
Firstpage
967
Lastpage
979
Abstract
An efficient algorithm is provided for solving a class of linear programming problems containing a large set of distance constraints of the form xi-xj⩾k and a small set of multivariable constraints of forms other than xi-xj⩾k. This class of linear programming formulation is applicable to very large scale integration (VLSI) layout spacing problems, including hierarchy-preserving hierarchical layout compaction, layout compaction with symmetric constraints, layout compaction with attractive and repulsive constraints, performance-driven layout compaction, etc. The longest path algorithm is efficient for solving spacing problems containing only distance constraints. However, it fails to solve problems that involve multiple-variable constraints. The linear programming formulation of a spacing problem requires use of the simplex method, which involves many matrix operations. This can be very time consuming when handling huge constraints systems derived from VLSI layouts. Herein it is found that most of the matrix operations can be replaced with fewer and faster graph operations, creating a more efficient graph-theory-based algorithm. Theoretical analysis shows that the proposed algorithm reduces the computation complexity of the simplex method
Keywords
VLSI; constraint theory; graph theory; integrated circuit layout; integrated circuit modelling; linear programming; VLSI layout spacing; computational complexity; distance constraints; graph theory; hierarchical layout compaction; layout compaction; linear programming; multiple variable constraints; simplex algorithm; Algorithm design and analysis; Compaction; Constraint optimization; Cost function; Linear programming; Upper bound; Very large scale integration; Wire;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.936378
Filename
936378
Link To Document