Stochastic Modeling-Based Variability Analysis of On-Chip Interconnects

In this paper, a novel stochastic modeling strategy is constructed that allows assessment of the parameter variability effects induced by the manufacturing process of on-chip interconnects. The strategy adopts a three-step approach. First, a very accurate electromagnetic modeling technique yields the per unit length (p.u.l.) transmission line parameters of the on-chip interconnect structures. Second, parameterized macromodels of these p.u.l. parameters are constructed. Third, a stochastic Galerkin method is implemented to solve the pertinent stochastic telegrapher´s equations. The new methodology is illustrated with meaningful design examples, demonstrating its accuracy and efficiency. Improvements and advantages with respect to the state-of-the-art are clearly highlighted.