Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers

Author

Ho, Yingchieh ; Chen, Hung-Kai ; Su, Chauchin

Author_Institution

Electr. Eng. Dept., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

2

Issue

2

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

307

Lastpage

313

Abstract

This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).

Keywords

CMOS integrated circuits; Monte Carlo methods; driver circuits; integrated circuit interconnections; repeaters; 3X predrivers; 4X predrivers; CMOS predriver; Monte Carlo analysis; SPRVT CMOS process; complementary metal oxide semiconductor; energy-effective sub-threshold interconnect; high-boosting predrivers; on-chip bus; repeater insertion; size 10 nm; size 65 nm; subthreshold region; voltage 0.15 V; Boosting; Clocks; Integrated circuit interconnections; Leakage current; Monte Carlo methods; Repeaters; Threshold voltage; Bootstrapped circuit; energy efficiency; gate boosting; interconnect; subthreshold circuit;

fLanguage

English

Journal_Title

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on

Publisher

ieee

ISSN

2156-3357

Type

jour

DOI

10.1109/JETCAS.2012.2193841

Filename

6198291