Optimized programming of multilevel flash EEPROMs

Author

Versari, Roberto ; Esseni, David ; Falavigna, Gianluca ; Lanzoni, Massimo ; Riccò, Bruno

Author_Institution

Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy

Volume

48

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1641

Lastpage

1646

Abstract

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 μm flash memory technology. It is shown that ramped gate programming provides tighter distributions of programmed threshold voltages than its conventional Box-Waveform counterpart, allowing one to write a larger number of b/s. In particular at low programming speed ramped gate programming is shown to allow four level schemes without program and verify operations, with a program bandwidth potentially approaching 30 Mb/s in the conventional 1-b-per-cell scheme (and correspondingly higher values in the multilevel case). Instead, sixteen level schemes without program and verify do not seem practically feasible

Keywords

PLD programming; circuit optimisation; flash memories; multivalued logic; 0.25 micron; 30 Mbit/s; dispersion; flash memory technology; multilevel flash EEPROMs; program bandwidth; programmed threshold voltages; ramped gate programming; speed; Bandwidth; Circuits; Data acquisition; EPROM; Flash memory; Latches; Nonvolatile memory; Performance evaluation; Testing; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.936581

Filename

936581