DC-gate-bias stressing of a-Si:H TFTs fabricated at 150°C on polyimide foil

We investigated the electrical stability of a-Si:H TFTs with mobilities of ~0.7 cm²/Vs fabricated on 51 μm thick polyimide foil at 150°C. Positive gate voltage V_g ranging from 20 to 80 V was used in the bias stress experiments conducted at room temperature. The bias stressing caused an increase in threshold voltage and subthreshold slope, and minor decrease in mobility. Annealing in forming gas substantially improved the stability of the TFTs. The threshold voltage shift exhibited a power law time dependence with the exponent γ depending on the gate bias V_g. For V_g=20 V, γ=0.45, while for V_g=80 V, γ=0.27. The threshold voltage shift also exhibited a power law dependence on V_g with the exponent β depending slightly on stress duration. β=2.1 for t=100 sec and 1.7 for t=5000 s. These values fall into the range experimentally observed for a-Si:H TFTs fabricated at the standard temperatures of 250-350°C