RF-CMOS performance trends

Author

Woerlee, Pierre H. ; Knitel, Mathijs J. ; Van Langevelde, Ronald ; Klaassen, Dirk B M ; Tiemeijer, Luuk F. ; Scholten, Andries J. ; Zegers-van Duijnhoven, Adrie T A

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

48

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1776

Lastpage

1782

Abstract

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed

Keywords

1/f noise; CMOS analogue integrated circuits; MOSFET; circuit simulation; field effect MMIC; integrated circuit design; integrated circuit modelling; integrated circuit noise; microwave field effect transistors; 1/f noise; 50 to 350 nm; MOS Model 11; MOS devices; RF circuit design; RF-CMOS performance trends; advanced validated compact model; analog performance; circuit simulations; cutoff frequency; drain bias conditions; gate bias conditions; limited linearity degradation; linearity; maximum oscillation frequency; noise figure; nominal gate length NMOS devices; power gain; scaling; scaling methodology; CMOS technology; Circuit simulation; Cutoff frequency; Linearity; MOS devices; Measurement; Noise figure; Performance gain; Radio frequency; Semiconductor device modeling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.936707

Filename

936707