Full CMP integration of CVD TiN damascene sub-0.1-μm metal gate devices for ULSI applications

Author

Ducroquet, Frédérique ; Achard, Hervé ; Coudert, Fabien ; Prévitali, Bernard ; Lugand, Jean-François ; Ulmer, Laurent ; Farjot, Thierry ; Gobil, Yveline ; Heitzmann, Michel ; Tedesco, Serge ; Nier, Marie-Elisabeth ; Deleonibus, Simon

Author_Institution

Lab d´´Electron. et de Technol. de l´´Inf., CEA, Centre d´´Etudes Nucleaires de Grenoble, France

Volume

48

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1816

Lastpage

1821

Abstract

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-μm gate transistors up to 0.6-mm² capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO₂)

Keywords

MOS capacitors; MOSFET; ULSI; chemical mechanical polishing; integrated circuit metallisation; integrated circuit reliability; semiconductor device metallisation; titanium compounds; tungsten; 0.1 mum; 0.1-μm gate transistors; 2 nm; CVD TiN film; MOS capacitors; MOS pattern structures; SiO₂; ULSI applications; ULSI circuit fabrication; W-TiN; W/TiN damascene metal gate; chemical mechanical polishing; damascene gate electrode; full CMP process integration; gate oxide integrity; nMOSFET; ultrathin gate oxide; uniform reliable electrical characteristics; Chemical processes; Chemical vapor deposition; Electric variables; Electrodes; Fabrication; Integrated circuit reliability; MOS capacitors; MOSFETs; Tin; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.936712

Filename

936712