DocumentCode
1514616
Title
N bit result integer multiplier with overflow detector
Author
Cha, Young Ho ; Cho, Gyeong Yeon ; Choi, Hyek Hwan ; Song, Hong Bok
Author_Institution
Div. of Electron., PuKyong Nat. Univ., Pusan, South Korea
Volume
37
Issue
15
fYear
2001
fDate
7/19/2001 12:00:00 AM
Firstpage
940
Lastpage
942
Abstract
This study is designed to suggest an N bit result integer multiplier with overflow detector indicating an N bit multiplication result and overflow status with an N bit multiplier and multiplicand input. The overflow is determined by the lower N bit result of multiplication and the number of leading sign bits of the multiplier and the multiplicand
Keywords
detector circuits; multiplying circuits; N bit result integer multiplier; multiplicand input; number of leading sign bits; overflow detection algorithm; overflow detector; signed integer multiplier;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010633
Filename
937289
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