A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to minimize the clock skew dynamically. Unlike most previous works that have focused on the implementation and the performance issues of a PST architecture, this paper focuses on the testing issues of a PST architecture. However, testing the variation tolerance ability of the PST architecture is difficult because the clock skew does not directly affect the functionality of a design. In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we propose some novel structures to detect the manufacturing faults and increase the robustness of a PST architecture. Our experiment shows that with a little increase in overhead, we can achieve robustness.